Senior RTL Design Engineer - BLR

Bangalore Avecas Technologies RTL Design 6+ yrs
Full-time

Job Description

Design high-performance CPU pipeline and cache subsystems in SystemVerilog. Drive micro-architecture optimization.

Required Skills

SystemVerilog CPU Pipeline Cache Micro-architecture
Domain
RTL Design
Location
Bangalore
Type
Full-time
Posted
Apr 24, 2026

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