Showing 1–20 of 165 positions
VLSI Intern - Malaysia
Digital Design basics
Verilog
EDA Tools
6-month internship program for fresh graduates. Learn VLSI design flow from RTL to GDSII with mentorship....
Verification Lead - Malaysia
UVM
SystemVerilog
Formal
Coverage
VCS
Team Leadership
Lead verification team for SoC projects in Malaysia design center. Define methodology, review testbenches, drive coverage and regression closure....
Trainee - Physical Design
VLSI basics
Digital Design
EDA Tool Basics
3-month intensive PD training for recent graduates. Learn netlist-to-GDSII flow using industry EDA tools. Guaranteed project placement....
VLSI Program Manager - US
ASIC Flow
Program Management
Cross-functional
Tapeout
Manage cross-functional VLSI programs from specification to tapeout. Coordinate global teams and drive milestone delivery....
Analog Design Engineer - UK
Spectre
Virtuoso
LDO
DCDC
PMIC
Automotive Analog
Design power management IPs (LDO, DCDC, PMIC) for European automotive customers at advanced FinFET nodes....
Layout Design Engineer - Digital
Virtuoso
Standard Cell
FinFET Layout
DRC
LVS
I/O Pads
ESD
Design standard cell and custom digital layouts for FinFET processes. Create library cells, I/O pads, and ESD cells with area optimization....
Staff RTL Design Engineer
SystemVerilog
Micro-architecture
Synthesis
Pipeline Design
Architect and implement high-performance CPU/GPU RTL. Lead micro-architecture trade-offs and mentor junior designers....
Library Characterization Engineer
Liberate
SiliconSmart
Liberty
SPICE
PVT
IO Char
Characterize standard cell and IO libraries across PVT corners. Generate Liberty timing models and validate accuracy....
Technical Recruiter - VLSI
LinkedIn Recruiter
ATS
VLSI Domain
Screening
Sourcing
Source and recruit VLSI semiconductor professionals. Screen candidates, manage ATS pipeline, and coordinate with engineering managers....
Principal Verification Engineer
UVM
Formal
Coverage
VCS
Xcelium
Regression
Drive chip-level verification strategy for complex SoCs. Own coverage closure, regression infrastructure, and silicon-quality signoff....
IP Integration Engineer - Malaysia
AMBA AXI
IP-XACT
Address Maps
SoC Integration
Integrate third-party and internal IP blocks into SoC designs. Handle AMBA bus configuration and interrupt routing....
Memory Design Engineer - US
SRAM
Memory Compiler
Bitcell
Characterization
Liberty
Design SRAM compilers and custom memory arrays for 3nm FinFET. Optimize bitcells for density, speed, and yield....
Senior Physical Design Engineer - Bangalore
Innovus
ICC2
PrimeTime
Floorplanning
CTS
Routing
FinFET
UPF
Lead PD implementation for FinFET designs including floorplanning, placement, CTS, routing, and timing closure at 7nm/5nm. Collaborate with design and DFT teams for tapeout....
Principal Verification Lead
UVM
Formal Verification
Coverage
Regression
Team Leadership
Lead chip-level verification closure with team of 8-12 engineers. Define strategy, methodology, and drive silicon-quality signoff including formal verification....
Power Integrity Engineer - Malaysia
RedHawk
Voltus
IR Drop
PDN
Power Grid
Analyze PDN for SoC designs. Perform IR drop analysis and power grid optimization for consumer SoCs....
Senior DFT Engineer - BLR
DFT Compiler
Tessent
Scan Compression
MBIST
JTAG
Implement DFT for complex SoCs targeting automotive and mobile markets. Drive 98%+ scan coverage and MBIST optimization....
Static Timing Analysis Engineer
PrimeTime
SDC
MCMM
AOCV
POCV
OCV
Clock Domain Crossing
Perform MCMM STA, develop timing constraints (SDC), and drive timing closure for SoC designs at sub-10nm nodes using advanced OCV methodologies....
Senior DFT Engineer - HYD
DFT Compiler
Tessent
Scan Compression
ATPG
JTAG
Lead DFT for SoC tapeouts. Define DFT architecture, manage scan compression, and drive test coverage optimization....
Senior Physical Design Engineer
Innovus
ICC2
PrimeTime
Floorplanning
CTS
Routing
FinFET
UPF
Lead block/chip-level PD implementation including floorplanning, placement, CTS, routing, and timing closure for FinFET designs at 7nm/5nm nodes. Drive PPA optimization and coordinate with DFT, packag...