Showing 101–120 of 165 positions
Signal Integrity Engineer - US
ANSYS HFSS
SIwave
Sigrity
PDN
DDR5 SI
PCIe Gen6
Perform SI/PI analysis for high-speed interfaces (DDR5, PCIe Gen6, USB4). Optimize PDN and package design....
RTL Design Engineer - Malaysia
Verilog
SystemVerilog
Synthesis
Lint
CDC
AMBA
Develop RTL for wireless and IoT SoC blocks. Perform lint, CDC, and synthesis for design handoff....
PDK Development Engineer
Virtuoso
Calibre
SKILL
PDK
Pcell
Liberty
SPICE Models
Develop and maintain PDKs including technology files, Pcells, DRC/LVS decks, and standard cell library characterization....
Reliability Engineer - US
JEDEC
AEC-Q100
ESD
Latchup
EM
NBTI
Failure Analysis
Drive IC reliability qualification per JEDEC/AEC-Q100 standards. Perform HTOL, ESD, latchup, EM, and NBTI analysis....
Technical Recruiter - UK
LinkedIn Recruiter
ATS
VLSI Domain
EU Sourcing
Source and recruit VLSI professionals across UK and Europe. Manage ATS pipeline and coordinate with engineering....
Senior Analog Layout Engineer - UK
Virtuoso
DRC
LVS
EM-aware
FinFET
PMIC Layout
Design complex analog/mixed-signal layouts for automotive PMICs. Ensure EM-safe, DRC/LVS clean layouts at FinFET nodes....
CAD/EDA Tool Engineer
Tcl
Python
Perl
Shell
Synopsys
Cadence
Mentor
Linux Admin
Develop EDA tool flows, automation scripts, and methodologies. Evaluate new tools, provide training, and maintain license/compute infrastructure....
Analog IC Design Engineer
Spectre
Virtuoso
SerDes
PLL
ADC
DAC
FinFET
Design high-speed SerDes, PLLs, and data converters for 5nm FinFET. Lead schematic design through post-layout verification....
Power Integrity Engineer - US
RedHawk
Voltus
IR Drop
EM
Decap
Power Grid
Analyze and optimize PDN for high-performance SoCs. Perform static/dynamic IR drop, EM analysis, and decap optimization....
CAD/EDA Manager - US
Synopsys
Cadence
Siemens
Tcl
Python
Linux
AWS
Lead EDA tool evaluation, deployment, and flow development. Manage compute infrastructure and license optimization....
Design Engineer - USB4/Thunderbolt
USB4
Thunderbolt
SerDes
CDR
CTLE
DFE
FinFET
Design USB4 and Thunderbolt PHY circuits including TX, RX, CDR, and equalization for 40Gbps+ data rates....
DFT Architect - US
DFT Compiler
Tessent
Scan Compression
MBIST
JTAG
Define DFT architecture for multi-billion gate SoCs. Lead scan, ATPG, MBIST strategy and coordinate with foundry test teams....
Verification Intern - Penang
Verilog basics
SystemVerilog
Digital Design
6-month internship in design verification. Learn UVM methodology and write testbenches under senior guidance....
Lead Verification Engineer - BLR
UVM
SystemVerilog
Formal
Coverage
VCS
Xcelium
Lead verification for SoC subsystems. Define strategy, build UVM environments, and drive coverage closure....
Place and Route Engineer
Innovus
ICC2
Placement
Routing
DRC
Multi-VT
Timing ECO
Tcl
Automated PnR for digital SoC designs. Drive placement optimization, routing closure, multi-VT optimization, and DRC-clean layouts....
SoC Integration Engineer - UK
AMBA AXI/ACE
IP-XACT
SoC Integration
TrustZone
Integrate CPU, GPU, NPU, and memory controllers into SoC designs. Handle AMBA interconnect and address map configuration....
CTS Engineer - BLR
Innovus CTS
ICC2 CTS
Clock Mesh
H-tree
Multi-source
Clock tree synthesis specialist for multi-clock SoCs. Design clock networks with optimized skew, latency, and power....
CDC/RDC Engineer - HYD
Spyglass CDC
Conformal CDC
RDC
Synchronizers
Perform CDC and RDC verification for multi-clock SoC designs. Ensure metastability-free operation across all modes....
Junior Physical Design Engineer
Innovus
ICC2
STA basics
DRC
LVS
Placement
Routing
Entry-level PD for 0-2 years experience. Assist in placement, CTS, routing, timing analysis, and DRC/LVS debugging under senior guidance....