Showing 81–100 of 165 positions
Senior Analog Layout - HYD
Virtuoso
SerDes Layout
ADC Layout
DRC
LVS
EM
Design layouts for high-speed SerDes and ADC IPs. Optimize for matching, parasitic control, and EM reliability....
Low Power Design Engineer
UPF
CPF
Power Gating
DVFS
Isolation
Retention
Multi-VDD
Implement multi-voltage domains, power gating, DVFS, and retention strategies for mobile and IoT SoCs using UPF 2.0 specification....
Physical Design Engineer - UK
Innovus
ICC2
CTS
Routing
DRC
LVS
Timing ECO
Execute PnR from netlist to GDSII for sub-10nm designs. Drive timing closure and DRC-clean layouts for tapeout....
RTL Design Engineer - HYD
SystemVerilog
AMBA AXI/AHB
Lint
CDC
Synthesis
Develop RTL for AMBA bus fabric and peripheral controllers. Perform lint, CDC analysis, and synthesis optimization....
Synthesis Engineer
Design Compiler
Genus
SDC
UPF
DesignWare
Low Power Synthesis
Perform RTL synthesis and optimization for area, timing, and power using Design Compiler or Genus. Develop synthesis constraints and methodology....
DFT Engineer - KL
DFT Compiler
TetraMAX
Scan
ATPG
MBIST
Implement DFT for consumer and IoT SoCs. Handle scan insertion, ATPG, and MBIST with high test coverage targets....
FPGA Design Engineer
Vivado
Quartus
Ultrascale+
DDR
PCIe
Verilog
VHDL
Implement RTL on Xilinx Ultrascale+ and Intel Stratix FPGAs for SoC prototyping. Perform synthesis, P&R, timing closure, and hardware debug....
SoC Architect
ARM
RISC-V
NoC
Memory Subsystem
Performance Modeling
Define next-gen SoC architectures for AI/ML edge devices. Lead performance modeling, IP selection, and interconnect design....
Verification Manager - HYD
UVM
Team Management
Strategy
Hiring
Delivery
Manage verification team of 10-15 engineers. Define strategy, drive hiring, and own project delivery milestones....
Project Manager - VLSI
ASIC Flow
Scheduling
Risk Management
Stakeholder Mgmt
PMP
Manage end-to-end VLSI project delivery. Coordinate cross-functional teams, track milestones, manage risks, report to leadership....
Test Engineer - ATE
Teradyne
Advantest
ATE Programming
Yield
Shmoo
Develop and optimize ATE test programs for production testing. Drive yield improvement and failure analysis on Teradyne/Advantest platforms....
Senior Project Manager - HYD
ASIC Flow
Program Mgmt
Multi-project
PMP
Agile
Manage multiple VLSI programs across domains. Drive resource planning, milestone tracking, and customer delivery....
Test Engineer - Malaysia
Teradyne
Advantest
ATE
Silicon Debug
Shmoo
Post-silicon validation and characterization on ATE platforms. Drive yield improvement and debug silicon failures....
Analog Design Engineer - Malaysia
Spectre
Virtuoso
Op-Amp
LDO
Bandgap
Sensor AFE
Design analog circuits for power management and sensor interface IPs. Support layout and post-silicon validation....
Senior Verification Engineer - Malaysia
UVM
SystemVerilog
Coverage
VCS
Xcelium
AMBA
Lead verification for SoC IPs. Develop UVM testbenches, drive coverage, and mentor junior engineers....
Senior Physical Design Engineer
Innovus
ICC2
PrimeTime
FinFET
UPF
CTS
Routing
Lead block-level PD for FinFET SoCs at 5nm/3nm. Drive floorplanning, placement, CTS, routing, and timing closure with PPA optimization....
Low Power Design Engineer - US
UPF 2.0
CPF
Power Gating
DVFS
Isolation
Level Shifters
Implement UPF-based multi-voltage designs with power gating, DVFS, and retention for mobile and wearable SoCs....
Functional Safety Engineer - US
ISO 26262
IEC 61508
FMEDA
FTA
ECC
Lockstep
ASIL-D
Implement ISO 26262 ASIL-D safety mechanisms for automotive SoCs. Lead FMEDA, FTA, and safety verification....
Floorplan Engineer
Innovus
ICC2
Floorplanning
Power Grid
Macro Placement
Package
Chip/block floorplanning specialist. Define die size, macro placement, power planning, pin assignment, and package coordination....