Senior Physical Design Engineer

San Jose Avecas Technologies Physical Design 8+ yrs
Full-time

Job Description

Lead block-level PD for FinFET SoCs at 5nm/3nm. Drive floorplanning, placement, CTS, routing, and timing closure with PPA optimization.

Required Skills

Innovus ICC2 PrimeTime FinFET UPF CTS Routing
Domain
Physical Design
Location
San Jose
Type
Full-time
Posted
May 11, 2026

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