Showing 41–60 of 165 positions
RISC-V Design Engineer - UK
RISC-V
Processor Design
Pipeline
SystemVerilog
Design RISC-V processor cores with custom extensions for European IoT and edge computing applications....
Staff SoC Architect
ARM
RISC-V
Interconnect
Memory Subsystem
Performance Modeling
Define next-generation SoC architectures for IoT and edge computing. Lead architecture trade-off studies (PPA), performance modeling, and IP selection strategy....
DFT Engineer - UK
DFT Compiler
Tessent
Scan
ATPG
MBIST
ISO 26262
Implement scan, ATPG, MBIST for automotive-grade SoCs. Coordinate with European foundry partners for test readiness....
STA Engineer - Malaysia
PrimeTime
SDC
MCMM
AOCV
ECO
Timing Closure
Perform multi-corner STA and drive timing closure for SoC designs. Develop timing constraints and ECO methodology....
Junior RTL Design Engineer - BLR
Verilog
SystemVerilog
Digital Design
Lint
Synthesis
Entry-level RTL design for 0-2 years experience. Develop Verilog/SV code for digital IP blocks under guidance....
Power Integrity Engineer
RedHawk
Voltus
IR Drop
EM Analysis
Decap
Power Grid
Multi-VDD
Analyze PDN for SoCs. Perform static/dynamic IR drop analysis, decoupling optimization, electromigration checks, and power grid design....
Static Timing Analysis Lead
PrimeTime
Tempus
SDC
AOCV
POCV
MCMM
SI-aware STA
Drive MCMM STA and timing closure for tapeout. Develop SDC constraints and advanced OCV methodology for sub-5nm designs....
Business Development Manager - UK
Semiconductor Sales
Automotive
BD
European Market
Drive VLSI design services business in UK and European semiconductor market. Build relationships with automotive OEMs and tier-1s....
Analog Layout Lead - BLR
Virtuoso
DRC
LVS
EM-aware
FinFET Layout
Team Lead
Lead analog layout team for mixed-signal IP development. Review layouts for matching, parasitic, and EM compliance....
AMS Design Engineer
Spectre
Virtuoso
SerDes
ADC
DAC
High-Speed I/O
FinFET
Design high-speed ADCs, DACs, SerDes PHYs, and I/O circuits for SoC integration at 7nm/5nm advanced technology nodes....
Functional Safety Engineer - BLR
ISO 26262
FMEDA
FTA
ECC
Lockstep
ASIL-D
Implement ISO 26262 safety for automotive SoCs. Perform FMEDA/FTA and define safety mechanisms at ASIL-B/D levels....
Trainee - RTL Design
Digital Design basics
Verilog
Logic Design
3-month intensive RTL design training for fresh graduates. Learn Verilog, SystemVerilog, and synthesis with project work....
Design Verification Engineer - Bangalore
UVM
SystemVerilog
Assertions
Coverage
VCS
Xcelium
AMBA
Build UVM testbenches, create coverage plans, and run regression for complex SoC IPs. Debug failures and drive coverage closure....
RISC-V Processor Design Engineer
RISC-V
RVV
Pipeline Design
SystemVerilog
ISA Extensions
Design custom RISC-V cores (RV64) with vector extensions for AI workloads. Optimize pipeline and implement custom ISA extensions....
Analog Layout Engineer
Virtuoso
DRC
LVS
Matching
Shielding
FinFET
ADC Layout
PLL Layout
Design analog/mixed-signal layouts for ADCs, DACs, PLLs, LDOs using Cadence Virtuoso at advanced FinFET nodes with optimized matching and parasitic reduction....
Power Grid Engineer - HYD
RedHawk
Voltus
IR Drop
EM
Power Grid
Decap
Design and optimize power distribution networks for SoCs. Perform IR drop analysis and electromigration checks....
Formal Verification Engineer - UK
JasperGold
VC Formal
SVA
CDC Formal
ISO 26262
Apply formal property checking and CDC/RDC verification for safety-critical automotive SoC designs....
Project Coordinator - Malaysia
Project Coordination
JIRA
Scheduling
Reporting
Coordinate VLSI project activities across Malaysia design center. Track deliverables and support project managers....
Floorplan Architect - HYD
Innovus
ICC2
Floorplanning
Power Grid
Package
Chip-level floorplanning for complex SoCs. Define die size, macro placement, power grid, and pin assignment....