Showing 61–80 of 165 positions
HR Manager - Malaysia
HR Management
Recruitment
Employee Relations
MYS Labor Law
Manage HR operations for Malaysia design center. Handle recruitment, onboarding, and employee relations....
Junior PD Engineer - BLR
EDA Tool Basics
Digital Design
Placement
Routing
Entry-level physical design. Assist in placement, CTS, routing, and timing analysis. Learn netlist-to-GDSII flow....
PDK Engineer - BLR
Virtuoso
Calibre
SKILL
PDK
Pcell
Liberty
SPICE
Develop and maintain PDKs for internal and customer use. Create Pcells, DRC/LVS decks, and characterize standard cells....
Synthesis Engineer - US
Design Compiler
Genus
SDC
UPF
DesignWare
Low Power
Perform RTL synthesis for area/timing/power optimization using DC/Genus. Develop synthesis methodology for complex SoCs....
Low Power Design Engineer - BLR
UPF
Power Gating
DVFS
Retention
Multi-VDD
Mobile
Implement UPF-based multi-voltage designs for mobile SoCs. Power gating, DVFS, retention, and isolation strategies....
Verification Manager - Cambridge
UVM
Formal
Team Management
Customer Delivery
Manage UK verification team. Drive strategy, resource planning, and milestone delivery for tier-1 semiconductor clients....
DFT Engineer - Malaysia
DFT Compiler
Tessent
Scan
ATPG
MBIST
ISO 26262
Implement DFT structures including scan insertion, ATPG, and MBIST for automotive-grade SoCs meeting ISO 26262 requirements....
RTL Design Lead - UK
SystemVerilog
Micro-architecture
Synthesis
Team Lead
Lead RTL team for IP development. Define coding guidelines, drive synthesis handoff, and mentor engineers....
Design Verification Engineer - UK
UVM
SystemVerilog
AMBA AXI
PCIe
Coverage
VCS
Build UVM testbenches for AMBA and PCIe protocol verification. Drive coverage closure for customer deliverables....
Staff Physical Design Engineer - BLR
Innovus
ICC2
PrimeTime
Full Chip PD
Tapeout
Signoff
Lead full-chip PD for high-performance compute SoCs at 5nm. Own floorplan-to-tapeout for production designs....
VLSI Training Lead - HYD
RTL
Verification
PD
DFT
EDA Tools
Curriculum
Design and deliver VLSI training programs covering RTL-to-GDSII flow. Develop curriculum and hands-on labs....
RTL Design Engineer - Bangalore
Verilog
SystemVerilog
Design Compiler
Genus
AMBA AXI
Lint
CDC
Develop synthesizable RTL in SystemVerilog for SoC IP blocks. Perform lint, CDC, synthesis, and work with verification teams for signoff....
Design Verification Engineer
UVM
SystemVerilog
Assertions
Coverage
VCS
Xcelium
AMBA
PCIe
Build UVM-based testbenches, develop coverage-driven verification plans, and ensure silicon-quality verification of complex SoC IPs including AMBA and PCIe protocols....
Physical Verification Engineer - US
Calibre
IC Validator
DRC
LVS
ERC
Antenna
Metal Fill
Run and debug DRC, LVS, ERC using Calibre and ICV. Own signoff quality for production tapeouts at advanced nodes....
CAD Engineer - Malaysia
Tcl
Python
Perl
Shell
Synopsys
Cadence
Develop and maintain EDA tool flows. Automate design tasks with Tcl/Python scripts. Support design teams....
DFT Engineer - Bangalore
DFT Compiler
TetraMAX
Tessent
Scan
ATPG
MBIST
JTAG
Implement scan, ATPG, MBIST, and JTAG for complex SoCs. Optimize test coverage and coordinate with foundry for test readiness....
Embedded Software Engineer - UK
C
C++
ARM
JTAG
SoC Peripherals
Linux BSP
Develop firmware and BSP for SoC validation. Write hardware diagnostic tests and support silicon bring-up....
Physical Design Engineer - Malaysia
Innovus
ICC2
PrimeTime
DRC
LVS
CTS
Routing
Tcl
Execute PnR flow from netlist to GDSII for sub-14nm designs. Handle placement, CTS, routing, and signoff closure....
FPGA Design Lead - BLR
Vivado
Quartus
Versal
Agilex
DDR5
PCIe Gen5
Lead FPGA prototyping for SoC designs on Xilinx Versal and Intel Agilex. Manage FPGA lab infrastructure....