Showing 121–140 of 165 positions
Timing Closure Engineer - UK
PrimeTime
Tempus
ECO
MCMM
SI-aware STA
Signoff
Drive timing closure from synthesis to signoff. Handle ECO generation and SI-aware STA for production tapeouts....
Senior Embedded Engineer - HYD
C
C++
ARM
JTAG
SoC Validation
Boot ROM
HAL
Develop SoC validation firmware and diagnostic software. Support silicon bring-up and characterization....
Technical Lead - AI Accelerator
AI Accelerator
NPU
Systolic Array
SystemVerilog
Design custom AI/ML accelerator hardware. Define architecture for inference engines and develop RTL implementation....
Senior Physical Design Engineer - UK
Innovus
ICC2
PrimeTime
FinFET
UPF
Automotive
Lead PD implementation for European automotive and consumer SoC projects at 7nm/5nm nodes. Drive PPA optimization....
Signal Integrity Engineer
ANSYS HFSS
SIwave
Sigrity
PDN
DDR SI
PCIe SI
USB SI
Analyze and optimize signal integrity for high-speed SoC and package interfaces. Perform SI/PI simulations and PDN design optimization....
Senior Analog Layout - Penang
Virtuoso
DRC
LVS
Matching
PLL Layout
ADC Layout
Design analog/mixed-signal layouts for data converters and PLLs. Optimize matching and minimize parasitics at advanced nodes....
Project Manager - UK VLSI
ASIC Flow
Scheduling
Risk Management
Customer Mgmt
Manage VLSI project delivery for UK and European clients. Track milestones, manage risks, and report to leadership....
Trainee - Design Verification
Digital Design basics
Verilog
Logic concepts
3-month DV training program. Learn UVM methodology, SystemVerilog, and verification concepts with hands-on labs....
Signal Integrity Engineer - BLR
ANSYS HFSS
SIwave
DDR5 SI
LPDDR5 SI
PDN Design
Perform SI/PI simulations for high-speed interfaces (DDR5, LPDDR5, PCIe). Optimize PDN and package design....
Embedded Firmware Engineer - Malaysia
C
C++
ARM
SoC Peripherals
UART
SPI
I2C
Develop firmware for SoC validation and production testing. Write HAL drivers and boot code....
Synthesis Engineer - Malaysia
Design Compiler
Genus
SDC
UPF
DesignWare
Perform RTL synthesis using DC/Genus. Optimize for area, timing, and power. Develop synthesis constraints....
Senior RTL Design Engineer - BLR
SystemVerilog
CPU Pipeline
Cache
Micro-architecture
Design high-performance CPU pipeline and cache subsystems in SystemVerilog. Drive micro-architecture optimization....
Staff Verification Engineer - HYD
UVM
Formal
Coverage
Regression
Signoff
Leadership
Drive chip-level verification closure for production SoCs. Own methodology, regression, and silicon-quality signoff....
ECO Engineer - HYD
Innovus ECO
ICC2 ECO
PrimeTime
Functional ECO
Handle engineering change orders for production SoCs. Implement metal-only and full ECOs to fix timing and functional bugs....
Business Development Manager - US
Semiconductor Sales
BD
Networking
Proposals
Negotiation
Drive business development for VLSI design services in the US semiconductor market. Build fabless company and IDM relationships....
Senior PD Engineer - HYD
Innovus
ICC2
PrimeTime
FinFET
Memory Controller PD
Lead block PD for memory controller and CPU subsystems at 5nm/3nm. Drive PPA optimization and timing closure....
Applications Engineer - US
VLSI
EDA Tools
Technical Sales
Solution Architecture
Provide pre/post-sales support for VLSI design services. Conduct technical demos, benchmarks, and develop solution architectures....
Design Engineer - PCIe/CXL
PCIe
CXL
SystemVerilog
Protocol Design
AMBA
Design PCIe Gen5/6 and CXL controller RTL. Implement protocol-compliant designs with comprehensive verification support....
Senior Analog Design Engineer - BLR
Spectre
Virtuoso
ADC
PLL
SerDes
FinFET Analog
Design high-speed ADCs, PLLs, and SerDes for SoC integration. Lead analog design reviews and tape-out....