Design Engineer - PCIe/CXL

Bangalore Avecas Technologies RTL Design 4+ yrs
Full-time

Job Description

Design PCIe Gen5/6 and CXL controller RTL. Implement protocol-compliant designs with comprehensive verification support.

Required Skills

PCIe CXL SystemVerilog Protocol Design AMBA
Domain
RTL Design
Location
Bangalore
Type
Full-time
Posted
Apr 23, 2026

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