Analog Layout Engineer

Hyderabad Avecas Technologies Analog Layout 4+ yrs
Full-time

Job Description

Design analog/mixed-signal layouts for ADCs, DACs, PLLs, LDOs using Cadence Virtuoso at advanced FinFET nodes with optimized matching and parasitic reduction.

Required Skills

Virtuoso DRC LVS Matching Shielding FinFET ADC Layout PLL Layout
Domain
Analog Layout
Location
Hyderabad
Type
Full-time
Posted
May 31, 2026

Apply Now

Fill in your details below to apply for this position
Back to All Jobs

Our Global Presence

Delivering VLSI excellence from five strategic locations worldwide

🇮🇳
Hyderabad, Telangana
India  ·  Headquarters
4th Floor, Radhe Heights,
Madhapur, Hyderabad 500081
🇮🇳
Bangalore, Karnataka
India
Design Center,
Bangalore 560001
🇺🇸
Sheridan, Wyoming
United States
30 N Gould St Ste R,
Sheridan, WY 82801
🇬🇧
Suffolk, England
United Kingdom
82A James Carter Road,
Mildenhall, Suffolk, IP28 7DE
🇲🇾
Penang
Malaysia
VLSI Design Center,
Penang, Malaysia