Senior Physical Design Engineer

Hyderabad Avecas Technologies Physical Design 8+ yrs
Full-time

Job Description

Lead block/chip-level PD implementation including floorplanning, placement, CTS, routing, and timing closure for FinFET designs at 7nm/5nm nodes. Drive PPA optimization and coordinate with DFT, packaging, and signoff teams.

Required Skills

Innovus ICC2 PrimeTime Floorplanning CTS Routing FinFET UPF
Domain
Physical Design
Location
Hyderabad
Type
Full-time
Posted
Jun 12, 2026

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