Principal Verification Engineer

San Jose Avecas Technologies Design Verification 12+ yrs
Full-time

Job Description

Drive chip-level verification strategy for complex SoCs. Own coverage closure, regression infrastructure, and silicon-quality signoff.

Required Skills

UVM Formal Coverage VCS Xcelium Regression
Domain
Design Verification
Location
San Jose
Type
Full-time
Posted
Jun 16, 2026

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