Principal Verification Lead

Hyderabad Avecas Technologies Design Verification 12+ yrs
Full-time

Job Description

Lead chip-level verification closure with team of 8-12 engineers. Define strategy, methodology, and drive silicon-quality signoff including formal verification.

Required Skills

UVM Formal Verification Coverage Regression Team Leadership
Domain
Design Verification
Location
Hyderabad
Type
Full-time
Posted
Jun 14, 2026

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