Junior Verification Engineer - BLR

Bangalore Avecas Technologies Design Verification
Full-time

Job Description

Entry-level DV for 0-2 years. Write UVM testbenches and run simulations under senior engineer mentorship.

Required Skills

Verilog SystemVerilog UVM basics Digital Design
Domain
Design Verification
Location
Bangalore
Type
Full-time
Posted
Jun 9, 2026

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