ASIC Verification Intern

Hyderabad Avecas Technologies Design Verification
Full-time

Job Description

6-month internship for final-year students. Learn UVM methodology, write testbenches, run simulations. Full-time conversion possible.

Required Skills

Verilog SystemVerilog basics Digital Design Simulation
Domain
Design Verification
Location
Hyderabad
Type
Full-time
Posted
Apr 4, 2026

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